Phase locked loops (PLLs) have important uses in communications applications. A PLL frequency synthesizer, one such use, generates an output signal having a programmable frequency to be used in tuning of two or more communication channels. Typically, a microprocessor programs the frequency of the output signal. In many applications, the programmed frequency must change dynamically. For example, the frequency normally generated by the PLL frequency synthesizer is used to tune a communications signal, but periodically the frequency must be changed to tune an auxiliary channel. The functioning of the phase locked loop may be enhanced by using a digital phase detector to measure a phase difference between the output signal and a proportion of a reference signal, and to adjust the output signal in response to a detected phase difference. Performance of PLL frequency synthesizers using digital phase detectors must continually be improved to meet increased performance requirements of communication circuits.